School of Informatics - University of Edinburgh Institute for Computing Systems Architecture - School of Informatics
Institute for Computing
Systems Architecture

ArcSim is our 'Swiss army knife' for high-speed functional and cycle accurate instruction set simulation of the EnCore processor. It provides various simulation modes and yields a wealth of statistics and metrics about simulated programs.

Simulation Modes

  • Cycle-Accurate Simulation mode allows for cycle-accurate simulation of our microarchitecture. This mode provides very detailed latency statistics for each instruction and has been calibrated using the EnCore processor.
  • Fast Cycle-Approximate Simulation mode enables fast prediction of cycle counts based on information gathered during fast functional simulation and prior training.
  • High-Speed Simulation mode uses Just-In-Time (JIT) Dynamic Binary Translation (DBT) techniques to create very high speed functional simulators capable of simulating an embedded system at speeds approaching (or even exceeding) real time. Recently we have extended our high-speed simulation mode with the capability of performing ultra-fast cycle accurate simulations by extending our JIT engine with the capability of augmenting JIT translated instructions with highly optimised cycle accurate code.
  • Co-Simulation mode provides a Co-Simulation API used for hardware and performance verification.
  • Register Tracking Simulation mode tracks read/write register access and the average distance (arithmetic mean, geometric mean) in instructions between a register access.

Other Features and APIs

  • API for Instruction Set Extensions: simple plugin API for declaring PASTA instruction set extensions.
  • API for Memory Mapped IO: simple and efficient API that allows one to hook custom code upon reads/writes to memory locations. We currently have the following implementation of memory mapped devices:
    • Screen device based on OpenGL and the GDK graphics library.
    • Memory mapped sound device utilising OpenAL as its sound backend.
    • A memory mapped UART implementation.
  • Emulation of System Calls: There are emulation implementations for many system calls as well as support for redirection of standard streams such as stdin, stdout, and stderr.
  • Debugging: Interactive debugging interface supporting single step tracing of instructions, debugging of processor state, setting of breakpoints, etc.


ArcSim Poster

ArcSim Instruction Set Simulator Poster