The EnCore C Compiler (or ECC) for our
ARC compatible EnCore processor
has been developed from scratch using the
CoSy compiler
construction toolkit. It serves as a research vehicle enabling us to
prototype and evaluate various code transformations improving code
size and energy efficiency whilst at the same time providing us with
an industrial-strength compilation environment equipped with a large
set of performance enhancing optimisation engines.
Among the features of the CoSy based EnCore C compiler are:
- Floating-point support. The compiler uses software emulation for floating-point operations.
- Mixed mode code generation. ARCompact 16bit instructions are intermixed with 32bit instructions. This results in higher code density (= smaller memory footprint) and better instruction cache behaviour (= higher performance and less energy).
- Zero-overhead loops. Hardware loops support efficient 'for' loop implementation and are generated wherever possible.
- Low-power/low-energy code optimisations. A set of code transformations aims at reducing the dynamic power consumption of our ultra-low power EnCore processor even further without introducing any performance penalty or relying on specific hardware support.
Publications
- T.Edler von Koch, I.Böhm and B.Franke.
Integrated Instruction Selection and Register Allocation for Compact Code Generation Exploiting Freeform Mixing of 16- and 32-bit Instructions
To appear in Proceedings of The International Symposium on Code Generation and Optimization (CGO '10), Toronto, Canada, April 2010.
