School of Informatics - University of Edinburgh Institute for Computing Systems Architecture - School of Informatics
Institute for Computing
Systems Architecture
Trace enabled RTL Co-Simulation using ModelSim

CoSim is our all-purpose tool for testing and verifying the EnCore Verilog chip design. It uses the Verilog Programming Language Interface (Verilog PLI) to interact with the internal representation of the design and the simulation environment.

In order to verify the execution of binaries CoSim uses ArcSim - the Golden Master reference model of the EnCore. The following listing outlines the basic concept of our CoSim simulation environment:

  • First a ELF binary is loaded into the functional simulator ArcSim and into the EnCore chip memory via the Verilog PLI interface.
  • Then instructions are executed in lock-step on the functional simulator ArcSim and within the hardware simulation environment (i.e. ModelSim)
  • After an instruction has committed, CoSim checks the hardware state against the Golden Master model state in ArcSim to verify the hardware implementation.

Hardware Simulation Levels

CoSim supports hardware simulation at the following levels of abstraction:

  • Register transfer level simulation
  • Full-timing (with Static Delay File) post-layout gate level simulation
We can also generate switching activity information at each of the abstraction levels using Switching Activity Interchange Format (SAIF) files that can in turn be used for power analysis.