School of Informatics - University of Edinburgh Institute for Computing Systems Architecture - School of Informatics
Institute for Computing
Systems Architecture

High Speed CPU Simulation using LTU Dynamic Binary Translation

    Paper - High Speed CPU Simulation using LTU Dynamic Binary Translation
  • Type: Paper
  • Authors:
    D. Jones and N.P. Topham.
  • Proc. 4th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC), Paphos, Cyprus, January 25-28, 2009.
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  • Abstract:

    In order to increase the speed of dynamic binary translation based simulators we consider the translation of large translation units consisting of multiple blocks. In contrast to other simulators, which translate hot blocks or pages, the techniques presented in this paper profile the target program’s execution path at runtime. The identification of hot paths ensures that only executed code is translated whilst at the same time offering greater scope for optimization. Mean performance figures for the functional simulation of EEMBC benchmarks show the new simulation techniques to be at least 63% faster than basic block based dynamic binary translation.