Cache Optimisations for Embedded Systems
On-chip memories, and caches in particular, consume a large fraction of the energy in embedded microprocessors. First level caches tend to dominate in terms of their dynamic power consumption, whereas second level caches often contribute significantly in terms of their static, or leakage, power. In many cases, the energy dissipated in first level caches alone is greater than or equal to the energy of the processor itself.
This research activity seeks to find ways to reduce the energy consumed by caches, particularly in embedded systems. We are currently looking at ways of dynamically configuring caches to reduce dynamic and static power, and expect initial results to be published later this year.
Our future plans include the use of new methods of dynamic adaptation, and new cache architectures to support such adaptation.
