Our paper titled Cooperative Partitioning: Energy-Efficient Cache Partitioning for High-Performance CMPs and written by K. Sundararajan, V. Porpodas, T. Jones, N. Topham and B. Franke, was accepted at the International Symposium on High Performance Computer Architecture (HPCA'12) in New Orleans, Louisiana.
This paper presents Cooperative Partitioning, a runtime partitioning scheme that reduces both dynamic and static energy while maintaining high performance. It works by enforcing cached data to be way-aligned, so that a way is owned by a single core at any time. Cores cooperate with each other to migrate ways between themselves after partitioning decisions have been made. We evaluate our approach on two-core and four-core systems, showing that we obtain average dynamic energy savings of 35% and static energy savings of 25% compared to a fixed partitioning scheme. In addition, Cooperative Partitioning maintains high performance while transferring ways five times faster than an existing state-of-the-art technique.
Our paper titled Generalized Just-In-Time Trace Compilation using a Parallel Task Farm in a Dynamic Binary Translator and written by I.Böhm, T.Edler von Koch, S. Kyle, B.Franke and N.Topham, was accepted at the ACM SIGPLAN 2011 Conference on Programming Language Design and Implementation (PLDI'11) in San Jose, CA.
In this work we have made advances in the area of trace-based compilation by proposing a novel tracing strategy, namely interval based tracing. Another significant advancement is the design and implementation of a truly parallel JIT compilation system based on the task farm design pattern. This parallel JIT compilation system is the first of its kind to successfully exploit the parallelism available on today's multi-core architectures, and to exploit the parallelism exposed by our novel tracing strategy.
The Engineering and Physical Sciences Research Council has announced funding of 1.2m over three and a half years for the PASTA-2 project. PASTA-2 is a new collaboration between researchers in the School of Informatics and the School of Engineering and Electronics at Edinburgh University, led by Prof Nigel Topham.
The overall objective of the PASTA-2 project is to investigate new and novel methods of automating the design of embedded systems to enable the timely creation of future generations of high-performance low-power digital appliances. This is an ambitious project, which brings together research in microprocessor design, software, signal processing, and an economically-important emerging application area.
"Embedded processors are an integral part of our everyday lives; from smart phones to wireless communications and bio-medical devices, future devices will require much higher performance than we have today, but their energy efficiency has to improve, as battery-life is critical".
Prof Nigel Topham
PASTA-2 Project Leader- School of Informatics at Edinburgh
Our paper titled Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator and written by I.Böhm, B.Franke and N.Topham, received the best paper award at the International Conference on Systems, Architectures, Modeling, and Simulation (IC-SAMOS'10).
M.Zuluaga and N.Topham also successfully submitted a paper to IC-SAMOS'10 titled Exploring the Unified Design-Space of Custom-Instruction Selection and Resource Sharing.
"MP3 players and 4G mobiles could be more energy efficient using the new EnCore microprocessor. It's smaller, faster and using 50 per cent less power than other commercial chips available, it helps extend battery life. Funded by EPSRC and developed by the University of Edinburgh, the microprocessor has been incorporated into a silicon chip and a working prototype has been tested."
MP3 players and 4G mobile phones could be more energy efficient thanks to a new versatile microprocessor. The microprocessor, known as EnCore, delivers faster processing while using significantly less power and taking up less space than comparable devices.
Researchers at the University of Edinburgh have incorporated the microprocessor into a silicon chip, and a working prototype has been demonstrated in the laboratory. The microprocessor is configurable - meaning that it can be automatically customised for a particular application, and so is suitable for a variety of gadgets. The adaptability of the processor means that performance is not compromised by energy efficiency.
"This is an important milestone for the project, as it demonstrates the research group's capability to produce working silicon from novel processor IP developed within the project. We are extremely pleased the design worked out-of-the-box in first silicon, and delighted with the chip's stability, operating frequency and low power consumption".
Prof Nigel Topham
PASTA Project Leader- School of Informatics at Edinburgh