In the PASTA group we believe that computer systems research should
address problems that will become important and have a significant
impact over a 5-10 year time-frame. This means developing new ideas
about how future processor architectures and their compilers should be created,
particularly about how one can search the complex design-space of synthetic
architectures and compilers automatically. However, this all relies
on the existence of experimental technologies for creating synthetic
processors and their tools.
Prior to the PASTA project, an experimental processor called
EnCore
was developed. This configurable single-issue RISC core implements the
ARCompact instruction set, which is typical of RISC processors used
in the embedded computing industry. EnCore exists in two flavours:
a 5-stage pipeline and and a 7-stage pipeline.
During the PASTA project, the EnCore processor has been refined and
integrated within a System-on-chip (SoC) framework from which real
silicon implementations can be derived. An extension interface has
been defined, allowing the results from research into
resource sharing and configurable function accelerators to be
integrated into this real system.
The EnCore processor and its SoC can be synthesized and run within an
FPGA platform.
This is currently based on the Xilinx Virtex-5 chip,
and the ML507 board. This allows us to operate the EnCore processor
at frequencies up to 75 MHz, and provides a range of I/O devices
that are accessible to software.
To enable us to create silicon from the EnCore processor, possibly
extended with synthetic instructions, we have developed a complete
RTL-to-GDSII design flow based on state-of-the-art EDA tools.
This ASIC flow allows members of the team to create production-worthy
silicon layouts of a complete chip in a few hours.
During the PASTA project a number of chips
are planned for production.
The first of these, code-named Calton, was taped-out in November 2008
to the UMC 0.13 micron high speed CMOS process.
This will allow us to calibrate our design metrics, including power
and performance, in real silicon. A test PCB
is being developed in conjunction with the
Institute for System Level Integration,
and will be available to the project in 2Q08.
The existence of the EnCore processor, its accompanying SoC design,
and the RTL-to-GDSII ASIC flow, enable us to undertake highly-realistic
research in topics such as power prediction and optimization,
synthesis of on-chip interconnects, and
cache optimisations.
As this work is based on real hardware and state-of-the-art tools and
silicon technologies, it will allow greater accuracy and relevance of results
compared with approaches based on high-level models.
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Institute for Computing Systems Architecture |
