Architecture/Micro-Architecture Synthesis
- Karthik T. Sundararajan, Timothy M. Jones, and Nigel P. Topham: The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Cache Adaptation [2013]
International Journal of Parallel Programming (IJPP '12), Volume 41, Issue 2, Special issue of best papers from SAMOS 2011, April 2013 - M.Zuluaga, E.Bonilla and N.Topham: Predicting Best Design Trade-offs: A Case Study in Processor Customization [2012]
Proceedings of Design, Automation and Test in Europe (DATE '12), March 2012. - K.Sundararajan, V.Porpodas, T.Jones, N.Topham and B.Franke: Cooperative Partitioning: Energy-Efficient Cache Partitioning for High-Performance CMPs [2012]
Proceedings of the 18th International Symposium on High Performance Computer Architecture (HPCA'12), New Orleans, US, February 25-29, 2012 - K.Sundararajan, T.Jones and N.Topham: Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency [2011]
Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS'11), Samos, Greece, July 19-22, 2011 - K.Sundararajan, T.Jones and N.Topham: A Reconfigurable Cache Architecture for Energy Efficiency [2011]
Proceedings of the ACM International Conference on Computing Frontiers (CF'11), Ischia, Italy, May 3-5, 2011 - M.Zuluaga and N.Topham: Exploring the Unified Design-Space of Custom-Instruction Selection and Resource Sharing [2010]
Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS'10), Samos, Greece, July 19-22, 2010 - M.Zuluaga, T.Kluter, P.Brisk, N.Topham and P.Ienne: Introducing Control-Flow Inclusion to Support Pipelining in Custom Instruction Set Extensions [2009]
In Proceedings of the 7th IEEE Symposium on Application Specific Processors (SASP '09), pages 114-21, San Francisco, CA, July 2009 - M.Zuluaga and N.P.Topham: Design Space Exploration of Resource Sharing Solutions for Custom Instruction Set Extensions [2009]
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD'09), volume 28, issue 12, pages 1788-1801, December 2009 - M.Zuluaga and N.P.Topham: Resource Sharing in Custom Instruction Set Extensions [2008]
IEEE Symposium on Application Specific Processors (SASP'08), Anaheim, CA, June 2008
ASIP Design Flow
- O.Almer, N.Topham and B.Franke: A Learning-Based Approach to the Automated Design of MPSoC Networks [2011]
Architecture of Computing Systems (ARCS '2011), Como, Italy, 2011 - A.Murray, R.V. Bennett, B.Franke and N.P.Topham: Code Transformation and Instruction Set Extensions [2009]
ACM Transactions on Embedded Computing Systems (TECS '09), volume 8, issue 4, 2009 - O.Almer, R.V.Bennett, I.Böhm, A.C.Murray, X.Qu, M.Zuluaga, B.Franke and N.P.Topham: An End-to-End Design Flow for Automated Instruction Set Extension and Complex Instruction Selection based on GCC [2009]
Proc. 1st International Workshop on GCC Research Opportunities (GROW'09), Paphos, Cyprus, 2009 - R.V.Bennett, A.C.Murray, B.Franke and N.P.Topham: Combining Source-to-Source Transformations and Processor Instruction Set Extensions for the Automated Design-Space Exploration of Embedded Systems [2007]
ACM SIGPLAN/SIGBED 2007 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego CA, June 2007
ASIP Compilation
- A.Murray and B.Franke: Compiling for Automatically Generated Instruction Set Extensions [2012]
Proceedings of the International Symposium on Code Generation and Optimization (CGO) - A.Murray and B.Franke: Adaptive Source-Level Data Assignment to Dual Memory Banks [2010]
ACM Transactions on Embedded Computing Systems (TECS) - T.Edler von Koch, I.Böhm and B.Franke: Integrated Instruction Selection and Register Allocation for Compact Code Generation Exploiting Freeform Mixing of 16- and 32-bit Instructions [2010]
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization (CGO '10), Toronto, Canada, April 2010 - A.C.Murray and B.Franke: Using Genetic Programming for Source-Level Data Assignment to Dual Memory Banks [2009]
Proceedings of the 3rd Workshop on Statistical and Machine Learning Approaches to Architecture and Compilation (SMART'09), Paphos, Cyprus, 2009 - A.Murray and B.Franke: Fast Source-Level Data Assignment to Dual Memory Banks [2008]
Proceedings of the Workshop on Software & Compilers for Embedded Systems (SCOPES'08), March 2008, Munich, Germany
Parallel Code Generation
- Tobias J. K. Edler von Koch and Björn Franke: Limits of region-based dynamic binary parallelization [2013]
International conference on Virtual Execution Environments (VEE '13), March 2013 - G.Tournavitis and B.Franke: Semi-Automatic Extraction and Exploitation of Hierarchical Pipeline Parallelism Using Profiling Information [2010]
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT '10), Vienna, Austria, September 11-15, 2010 - G.Tournavitis, Z.Wang, B.Franke and M.O'Boyle: Towards a Holistic Approach to Auto-Parallelization: Integrating Profile-Driven Parallelism Detection and Machine-Learning Based Mapping [2009]
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'09), Dublin, Ireland, June 15 - G.Tournavitis and B.Franke: Towards Automatic Profile-Driven Parallelization of Embedded Multimedia Applications [2009]
Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG'09), Paphos, Cyprus, January 25
High-Speed Simulation and Performance Prediction
- Christopher Thompson, Miles Gould and Nigel Topham: High speed cycle approximate simulation for cache-incoherent MPSoCs [2013]
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS '13), July 2013 - Oscar Almer, Igor Böhm, Tobias Edler von Koch, Björn Franke, Stephen Kyle, Volker Seeker, Christopher Thompson and Nigel Topham: A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation [2013]
International Journal of Parallel Programming (IJPP '12), Volume 41, Issue 2, April 2013 - Harry Wagstaff, Miles Gould, Björn Franke, and Nigel P. Topham: Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description [2013]
Proceedings of the 50th Annual Design Automation Conference (DAC '13), June 2013 - S.Kyle, I.Böhm, B.Franke, H.Leather and N.Topham: Efficiently Parallelizing Instruction Set Simulation of Embedded Multi-Core Processors Using Region-based Just-in-Time Dynamic Binary Translation [2012]
To appear in Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES'12), Beijing, China, June 12-13, 2012 - I.Böhm, B.Franke and N.Topham: Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator [2011]
Transactions on High-Performance Embedded Architectures and Compilers (HiPEAC'11), Volume 5, Issue 4, 2011 - O.Almer, I.Böhm, T.Edler von Koch, B.Franke, S.Kyle, V.Seeker, C.Thompson and N.Topham: Scalable Multi-Core Simulation Using Parallel Dynamic Binary Translation [2011]
Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS'11), Samos, Greece, July 19-22, 2011 - I.Böhm, T.Edler von Koch, S. Kyle, B.Franke and N.Topham: Generalized Just-In-Time Trace Compilation using a Parallel Task Farm in a Dynamic Binary Translator [2011]
ACM SIGPLAN 2011 Conference on Programming Language Design and Implementation (PLDI'11), San Jose, CA, June 2011 -
I.Böhm, B.Franke and N.Topham: Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator [2010]
Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS'10), Samos, Greece, July 19-22, 2010 - B. Franke: Statistical Performance Modeling in Functional Instruction Set Simulators [2010]
ACM Transactions on Embedded Computing Systems (TECS) - D. Powell and B. Franke: Using Continuous Statistical Machine Learning to Enable High-Speed Performance Prediction in Hybrid Instruction-/Cycle-Accurate Instruction Set Simulators [2009]
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), Grenoble, France, October 11-16, 2009 - D. Jones and N.P. Topham: High Speed CPU Simulation using LTU Dynamic Binary Translation [2009]
Proc. 4th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC), Paphos, Cyprus, January 25-28, 2009 - B.Franke: Fast Cycle-Approximate Instruction Set Simulation [2008]
Proceedings of the Workshop on Software & Compilers for Embedded Systems (SCOPES'08), March 2008, Munich, Germany - N.P. Topham and D. Jones: High Speed CPU Simulation using JIT Binary Translation [2007]
The 3rd Annual Workshop on Modeling, Benchmarking and Simulation, held in conjunction with ISCA-34, San Diego CA - R.Hassan, A.Harris, N.P.Topham and A.Efthymiou: Synthetic Trace-Driven Simulation of Cache Memory [2007]
The 4th IEEE International Symposium on Embedded Computing (SEC'07), Niagara Falls, Canada, May 2007 - R.Hassan, A.Harris, N.P.Topham and A.Efthymiou: A Hybrid Markov Model for Accurate Memory Reference Generation [2007]
IAENG Int. Conf. on Computer Science (ICCS'07), Hong Kong, Mar. 2007
