A LLVM Backend for a Just-In-Time Compilation Engine of a state-of-the-art Instruction Set Simulator
Instruction Set Simulators as well as Virtual Machines implement JIT compilation techniques for improving the runtime performance of computer programs. The idea is to convert code compiled for some different architecture into native machine code at runtime to increase simulation speed. As part of the PASTA project a state-of-the-art ISS for the ARC© instruction set architecture implementing JIT compilation techniques has already been developed. The aim of this project is to extend the current JIT compilation engine with a LLVM (Low Level Virtual Machine) backend to decrease JIT compilation time whilst generating fast code.
The full specification is available at: Project Specification
Supervisors: Björn Franke, Nigel Topham
Concurrent, Adaptive, Just-In-Time and Ahead-Of-Time Compilation in the context of a state-of-the-art Instruction Set Simulator
Instruction Set Simulators as well as Virtual Machines implement JIT compilation techniques for improving the runtime performance of computer programs. The idea is to convert code compiled for some different architecture into native machine code at runtime to increase simulation speed. As part of the PASTA project a state-of-the-art ISS for the ARC© instruction set architecture implementing JIT compilation techniques has already been developed. The aim of this project is to extend the current JIT compilation engine with a concurrent and adaptive JIT compilation engine in order to better utilise todays multi-core architectures. Furthermore the new JIT compilation engine should be extended to support AOT compilation to enable even faster simulation speeds.
The full specification is available at: Project Specification
Supervisor: Björn Franke
Customisation of an extensible, ultra-low power embedded RISC processor
Extensible processors are application-specific
instruction set processors (ASIPs) that allow for customisation
through user-defined instruction set extensions (ISE)
implemented in an extended micro architecture.
The EnCore processor is developed entirely within the
Institute for Computer Systems Architecture (ICSA) at the University
of Edinburgh. The core is written in Verilog, and currently exists as
two main variants; five and seven stage pipeline depth
versions, each having varying cache configurations. Both
feature a reasonably complete implementation of the ARCompact
instruction set (as defined by the commercial ARC700
core), to the point that the arc-elf32 version of GCC can be used for
compilation of C code for the processor. The EnCore does not currently
feature an MMU, but this is in development and is likely to be
incorporated into a later version of the EnCore.
The EnCore has been tested with various configurations in
FPGA fabric, and has through this method been verified as
correctly executing compiled C code obtained through the GCC arc-elf32
compiler. The five stage core closes timing at 25MHz using
a Spartan-3 1600E FPGA as the implementation fabric, utilising
approximately 50% of the available resources, and is expected to run
two or three times faster using a newer FPGA family. The seven stage
pipeline variant is expected to tolerate a roughly 40% higher clock
frequency than this.
The core can be extended using modules written in Verilog derived from
the ISEs. While it is expected that these will increase the logic in
the core, in some cases by a large factor, we are not expecting it to
impact the maximum operating frequency to a large degree. ISEs
incorporated do not affect the critical path of the core
itself, and are timed to fit with the clock frequency of
the main core pipeline.
The student will go through the full processor customisation flow for
a compute-intensive numerical application and evaluate the performance
improvement over the existing processor/application baseline implementation.
Supervisors: Björn Franke, Nigel Topham
Energy-efficient Data Caches for Embedded Microprocessors
Cache memories account for over half the total power consumption of a
typical embedded microprocessor. Hence, even relatively simple energy
saving schemes can have a big impact on overall energy efficiency. In
an M-way set-associative data cache there are M tag memories and M
data memories. A naive data cache implementation will access all 2M
memory devices simultaneously, every time a Load or Store instruction
is executed. To counter this problem, 'way prediction' schemes have
been devised. These attempt to predict the 'way' in which the required
data resides (assuming it is in cache). If the prediction mechanism is
correct, approximately 1-(1/(2M)) of the memory-related energy is
saved. If the prediction is incorrect, the energy increases slightly
and the program may see a performance penalty. The aim of this project
is to evaluate the energy saving potential of one or more
'conservative' methods that either yield a perfect prediction or no
prediction at all. Such schemes already exist. This will require the
construction of a trace-driven simulator through which the prediction
accuracy of various schemes can be determined. As an extension, the
best-performing scheme could be implemented in an existing synthesised
embedded microprocessor.
Supervisors: Nigel Topham,Aris Efthymiou
Optimising Branch Predictors for Low-power Embedded Processors
A high-speed simulator is available in Informatics for research
purposes. One interesting research question that could be addressed by
this simulator, is how to trade Branch Predictor accuracy for energy
consumption in embedded systems. This project will use an exisisting
simulation framework that is able to simulate Linux running at around
200 MIPS. The project will deploy a range of Branch Predictors and
measure their effective prediction accuracy when running realistic
workloads. The energy consumption of each predictor can be estimated
using simple linear models, and from this it will be possible to gain
insight into the most effective predictors in such embedded
systems. In particular, the interference between operating system and
application will be measurable in this very realistic simulation.
Supervisors: Nigel Topham, Marcelo Cintra
