Our EnCore ASIC design flow depicts the flow from standard Verilog to the final chip design ready for tape-out. Once certain constraints and design rules have been specified, the flow is fully automatic. The following image shows the ASIC flow on a very abstract level:
A much more detailed image of the ASIC flow describing each step in detail is the following:
Click on the image below to get a detailed ASIC flow version in PDF format scaled for A0:
