Design Space Exploration of Resource Sharing Solutions for Custom Instruction Set Extensions
- Type: Paper
- Authors:
M.Zuluaga and N.P.Topham. - In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD'09), volume 28, issue 12, pages 1788-1801, December 2009.
- Download as PDF
-
Abstract:
Customized processor performance generally in- creases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency are equally important. Resource sharing during synthesis of Instruction Set Extensions (ISEs) can significantly reduce the die area and energy consumption of a customized processor. This may increase the number of custom instructions that can be synthesized with a given area budget. Resource sharing involves combining the graph representations of two or more ISEs which contain a similar sub-graph. This coupling of multiple sub-graphs, if performed naively, can increase the latency of the extension instructions considerably. And yet, as we show in this paper, an appropriate level of resource sharing provides a significantly simpler design with modest increases in average latency for ISEs. Our main contributions are the introduction of a parametric method for exploring the trade-offs that can be achieved between instruction latency and implementation complexity, and the coupling of design-space exploration with fast area-delay models for the operators comprising each ISE. We present experimental evidence that our heuristic exposes a broad range of design points, allowing advantageous trade-offs between die area and latency to be found and exploited.
