School of Informatics - University of Edinburgh Institute for Computing Systems Architecture - School of Informatics
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A Reconfigurable Cache Architecture for Energy Efficiency

    Paper - A Reconfigurable Cache Architecture for Energy Efficiency
  • Type: Paper
  • Authors:
    K.Sundararajan, T.Jones and N.Topham.
  • Proceedings of the ACM International Conference on Computing Frontiers (CF'11), Ischia, Italy, May 3-5, 2011.
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  • Abstract:

    On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time re- configuration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18% better than state-of-the-art reconfiguration architectures.