Towards a Grid-Enabled Simulation Framework for Nano-CMOS Electronics

The electronics design industry is facing major challenges as transistors continue to decrease in size.
The next generation of devices will be so small that the position of individual atoms will affect their behaviour.
This will cause the transistors on a chip to have highly variable characteristics, which in turn will impact
circuit and system design tools. The EPSRC project “Meeting the Design Challenges of Nano-CMOS
Electronics” (Nano-CMOS) has been funded to explore this area. In this paper, we describe the
distributed data-management and computing framework under development within Nano-CMOS. A
key aspect of this framework is the need for robust and reliable security mechanisms that support distributed
electronics design groups who wish to collaborate by sharing designs, simulations, workflows, datasets and
computation resources. This paper presents the system design, and an early prototype of the project which hasbeen useful in helping us to understand the benefits of such a grid infrastructure. In particular, we also present two typical use cases: user authentication, and execution of large-scale device simulations.